There are two conventional methods for manufacturing Flip-Chip Chip-Scale Package as shown in FIGS. 1A to 1D and 2A to 2D. The Flip-Chip Chip-Scale Package, a three dimension package technology strides toward high-power, high-density and lightweight miniaturized to meet the demand for communication products. Basically, the manufacturing method can be divided into two stages, carrier board stage and package stage. When a die is formed to be a package structure after the two stages, the package structure can be a main structure of a package-on-package, up or down connecting to other package structure or printed circuit boards.
With the referenced to FIGS. 1A to 1D, the package stage of the Flip-Chip Chip-Scale Package includes the steps below:
a) providing a carrier board 10 larger or equaling to 150 um having a plurality of first and second contact points 11, 12 at an upper surface thereof and a third contact point 13 at a lower surface thereof; having the second contact point 12 located around the first contact points 11 and planting a first ball 16 at the second contact point 12;
b) providing at least one die 14 having an active surface 141 and a non-active surface 142; providing a plurality of dumps 143 arranged at the active surface 141 and bonded to the first contact point 11; reflowing the carrier board 10 with die 14 through a flux for fixing the die 14 on the carrier board 10; removing the flux after finishing reflowing and utilizing capillary to underfill a primer 15 between the die 14 and the carrier board 10;
c) providing a first ball 16 mounted to the second contact point 12; over laying the first ball 16 and the die 14 by a package molding material 17 for package molding;
d) providing a second ball 18 mounted to the third contact point 13 and conducting Through Mild Via at a predetermined position of the package molding material 17 by laser for presenting an exposed state at a top of the first ball 16.
With the referenced to FIGS. 2A to 2D, the package stage of the Flip-Chip Chip-Scale Package includes the steps below:
a) providing a carrier board 10 larger or equaling to 150 um having a plurality of first and second contact points 11, 12 at an upper surface thereof and a third contact point 13 at a lower surface thereof; having the second contact point 12 located around the first contact points 11 and planting a first ball 16 at the second contact point 12;
b) providing at least one die 14 having an active surface 141 and a non-active surface 142; providing a plurality of dumps 143 arranged at the active surface 141 and bonded to the first contact point 11; reflowing the carrier board 10 with die 14 through a flux for fixing the die 14 on the carrier board 10 and removing the flux after finishing reflowing;
c) providing package molding material 17 over laying the first ball 16 and bonding to both sides of the die 14 and between the die 14 and the carrier board 10 to present an exposed state at an upper surface of the die 14 for package molding;
d) providing a second ball 18 mounted to the third contact point 13 and conducting Through Mild Via at a predetermined position of the package molding material 17 by laser for presenting an exposed state at a top of the first ball 16.
The above two manufacturing methods of the Flip-Chip Chip-Scale Package use the Through Mild Via structure as the mainstream of the Flip-Chip Chip-Scale Package products. Due to the supporting action while reflowing and the warpage problems of the carrier board 10, the core thickness of the carrier board 10 requires more than 150 um, resulting in the fact that the total thickness of the carrier board 10 cannot be reduced and therefore the Through Mild Via structure formed by the method of the Flip-Chip Chip-Scale Package hinders the total thickness of the package products of the Package-on-Package from continuously declining, being unable to meet future demands of miniaturization. Therefore, there is a still room for improvements.
Also, in U.S. Pat. No. 5,521,435, Mizukoshi disclosed a semiconductor device including a package baseplate 40, a semiconductor chip on the package baseplate 40, a jumper baseplate 40 carrying electrodes thereon and conductor patterns that connect the electrodes. The jumper baseplate 40 is mounted upon the package baseplate 40 to provide an interconnection between the electrode patterns on an upper surface of the package baseplate 40 in electrical connection with the electrode pads on the semiconductor chip and the electrodes that are isolated corresponding to a plurality of through-holes arranged on the package baseplate 40. The semiconductor device further has an opening filled with resin to encapsulate the semiconductor chip.